1. Field of the Invention
The present invention relates to an insulated gate field effect transistor and an integrated circuit built therefrom, and more specifically, to a technique which uses for a channel formation region a semiconductor thin film such as SOI (Semiconductor On Insulator) or SON (Semiconductor On Nothing). The semiconductor thin film is formed on an insulating substrate (SOI) in some cases, is suspended and held at both ends by substrates in a hollow state (SON) in some other cases, and has a projecting portion which is connected at one end to a substrate in still other cases.
2. Description of the Related Art
A method called a dynamic threshold voltage controlling method has been proposed as a measure to obtain high speed and low stand-by power consumption by keeping the absolute value of the gate threshold voltage large to reduce leak current of a transistor when it is not in operation whereas keeping the absolute value of the gate threshold voltage small when it is in operation.
The dynamic threshold voltage controlling method is made implementable by connecting a well to a gate electrode if the transistor is a bulk MOS transistor formed on a semiconductor substrate and by connecting a body to a gate electrode if the transistor is a partially depleted SOI MOS transistor, so that the gate electrode serves as a signal input terminal (Reference 1: F. Assadeargi, et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation” AIEEE Electron Device Letters, Vol. 15, No. 12, pp. 510-512, December, 1994).
The term partially depleted SOI, abbreviated as PD SOI, refers to SOI in which a depletion layer spreads only partially in the depth direction of its semiconductor thin film to give it a neutral region. ‘Body’ is a simplified term for the above semiconductor thin film in which a channel is formed.
On the other hand, SOI in which a combination of the thickness and impurity concentration is such that the depletion layer covers the entire depth of the semiconductor thin film is called FD (fully depleted) SOI. In FDSOI, within a certain gate voltage range, the body under a gate is depleted for the entire depth to provide no neutral region. Therefore, unlike bulk MOS and PDSOIMOS, connecting the body to the gate and inputting an ON signal thereto does not help FDSOI much in controlling the absolute value of the threshold voltage of the transistor. This is because forward bias between a source and a portion of the body that forms a channel is difficult to achieve when the body is depleted.
A patent on an insulated gate transistor structured to sandwich a semiconductor between two conductive gates through air gaps was granted in U.K. in 1935 to o. Heil. However, it did not mention or even hinted that a transistor having this structure is applicable to prevent so-called short channel effect in a micro-channel transistor.
In contrast, a transistor structure in which a fully depleted (FD) semiconductor thin film is sandwiched between a first conductive gate and a third conductive gate with a gate insulating films has been proposed by an inventor, for the first time in the record, as a measure to overcome the limit of miniaturization of single gate MOS transistors which have come into practical use in recent years. The name the inventor has given to a transistor that has this structure is XMOS transistor (Reference 2: T. Sekigawa, Y. Hayashi, K. Ishii, S. Fujita, “MOS Transistor for a 3D-IC”, A 17th Conference on Solid State Devices and Materials, Tokyo, 1985, Final Program and Late News Abstract, C-3-9 LN, pp. 14-16. Reference 3: Hayashi, “A Guide to Device Design Effective in the Coming Age of 0.025 μm”, Nikkei Microdevice July 1988, pp. 121-125.). Lately, many have published the fruition of their miniaturization research by the name of double gate MOS transistor.
Transistors having this structure are known to be capable of changing the gate threshold voltage viewed from a first gate by the electric potential of a third conductive gate. However, when the electric potential of the third conductive gate is fixed, the sub-threshold slope is increased and the ON-OFF transition voltage becomes large to give these transistors a drawback of poor switching efficiency. In addition, the method of controlling the threshold voltage solely by the third conductive gate electric potential has a drawback that the variable range of the threshold voltage is too limited. Another problem of this method is that, when applied to the SOI structure and the like in which the third conductive gate is placed on the back side of the semiconductor thin film, the method requires excess area and process steps for taking out an electric connection wire from the third conductive gate of each transistor.